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DsPIC Block/UART Configuration

From - Simulink device driver Blockset for dsPIC / PIC24 / PIC32 Microcontrollers --[[User:LubinKerhuel|LubinKerhuel]] 12:40, 3 September 2009 (UTC)
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Block UART Configuration

The UART Configuration block set the parameters for the UART. Each UART has one Receive Rx pin and one Transmit pin Tx. The UART parameters are commmon for Rx and Tx of the same UART. The number or UART available depend on the Microcontroller used ( defined in the master block). Following parameters are fixed :

  • 1 stop bit
  • 8 bits data
  • no parity
  • no flow control

Dialog Box Parameters


UART to be used

Baud (kb/s)

UART Speed you want to use. The exact speed will usually not be reach. An error above 4% usually gives no transmission errors. Check the error speed before use.

Tx Rx Alternativ

Use the Alternative Tx and Rx pin of the microcontroller if available. Use default pin otherwise.

Tx Interrupt Priority

Tx Interrupt are used when the block "Tx Output Multiplexed For Matlab Labview" is present. This block stores input into a circular buffer. The Tx interrupt get datas from this buffer.

Tx Interrupt

The Microcontroller has an internal 4 bytes buffer TXBUF. "Interrupt on TXBUF becoming empty" will gives fewer but longer interrupt."Interrupt on transfer of every character to TSR" will fullfill the microcontroller internal buffer as soon as there is one empty place. This will result in more interrupts.


Set the output pin TX active for transmitting serial data. This is automatically checked when a Tx or "Tx Output Multiplexed For Matlab Labview" is present.

RX Interrupt Priority

Interrupt Priority


Gives following information : UxBRG register value. The real bit rate achieved by the microcontroller and the error in percent between the real bit rate and the requested bit rate. The max Byte/Step is the maximum number of byte that can physically be sent during one diagram time step. If your schematic send more data throw the UART, somme data will be lost or the real time constraint will be violated (ie, the time step will be longer than expected).