PLL does not seem to work correctly (bug report)
Posted: Wed Aug 08, 2007 3:36 pm
When using the Explorer demo with a crystal frequency between 8 and 16 MHz only the base clock functions correctly. When the PLL is ticked a divide by zero error occurs on the matlab command line. The mask shows zero for instructions, and prescaler says NaN. I was trying to get 40MIPS with the 8 MHz crystal which is within the allowable range of "FIN must be chosen to be in the range of 1.6 MHz to 16 MHz" (from data sheet). Could you have a look at this? Maybe I'm using the mask incorrectly?
By the way, Keep up the good work. I have been using rtw and embedded coder for years and this target is very well done
Im using the MC variation of the 33 series any plans to add these devices/ drivers?
By the way, Keep up the good work. I have been using rtw and embedded coder for years and this target is very well done
Im using the MC variation of the 33 series any plans to add these devices/ drivers?