frequency mismatching

Deepthi
Posts: 3
Joined: Fri Nov 27, 2009 4:34 am

frequency mismatching

Postby Deepthi » Fri Nov 27, 2009 4:41 am

Hi Lubin,

Your blockset is amazing and i am using the trial version of Matlab_09a .My problem is that i am not getting the frequency of square pulse correctly once i download the hex file to dsPIC.The frequency in the model is correct,problem is with the hardware.I am using dsPIC30f3011.I am using a 20mHz crystal oscillator as clock.What can be the problem?

Thank you

Deepthi.

LubinKerhuel
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Re: frequency mismatching

Postby LubinKerhuel » Fri Nov 27, 2009 10:24 am

Hi Deepthi,

Please upload the model you made (adding screenshoot is even better). this will help to identify the problem.

On 30f chip, the real MIPS is the frequency of the quartz divided by 4, and then multiplied with the choosen PLL (1 if no PLL) . See help http://www.kerhuel.eu/wiki/Block/Master

Lubin

Deepthi
Posts: 3
Joined: Fri Nov 27, 2009 4:34 am

Re: frequency mismatching

Postby Deepthi » Wed Dec 09, 2009 5:12 pm

Hi Lubin

Sorry for the late reply.Actually i tried with correct MIPS,but i am still having the same problem.I am attaching the model with this post.Please help me out!

Deepthi
square4.mdl
a square pulse of 20ms
(26.91 KiB) Downloaded 129 times

LubinKerhuel
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Re: frequency mismatching

Postby LubinKerhuel » Wed Dec 09, 2009 6:03 pm

Hi Deepthi,

Do you get a slower frequency ? could you describe, what are you seeing on your scope ?

I do not see obvious errors on the model configuration
BUT
you selected a time step of 0.00001 which is 100Khz. That's very fast and perhaps the dspic cannot execute the mode that fast ! It may append that each time step will takes about 15us instead of 10us.
You can check if real time constraint with the busy flag port and the overload flag port in the master block. You could also have more precision using the Time Step block

To correct the problem quickly, 3 solutions :
- reduce the time step of your model (use for example .001 for 1Khz)
- increase the dsPIC MIPS with a pll
- generate a PWM pulse using Output Compare of PWM motor block (if available on this dsPIC) (however, with this solution, you should check anyway that real time constraints are OK otherwise your algorithm'll will not be correct : for example filter frequency cut will not be the one expected...)

Lubin

Deepthi
Posts: 3
Joined: Fri Nov 27, 2009 4:34 am

Re: frequency mismatching

Postby Deepthi » Thu Dec 10, 2009 4:25 am

Hi Lubin,

Thanks for the reply.I will try out as you said and reply to you as soon as possible.But when i tried to make the fixed step size as 1ms.Its showing the error that the "period must be an integer multiple of the fixed step size".What can be the reson for this??

Deepthi

LubinKerhuel
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Posts: 616
Joined: Wed Mar 07, 2007 11:23 pm
Location: Marseille - France
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Re: frequency mismatching

Postby LubinKerhuel » Thu Dec 10, 2009 9:42 am

This error means that a block is configured to run with a sampling rate that is either faster, or not an integer multiple of the the model sampling rage.

In your model, the block Convert is defined with a sampling rate of 0.0001s. I would advise to set this block to -1 to get it working at the same sampling rate as the Pulse Generator connected to it.

This "wrong" sampling rate could also be the cause of the bad result you get when the model was configured with a sampling rate of 0.00001s.
Please have a look on model time-step and sampling rate topics in simulink help page, you will find many usefull information here that should be better than any of my explanations...

Lubin


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