Question about SPI

LubinKerhuel
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Question about SPI

Postby LubinKerhuel » Wed Apr 30, 2008 11:10 pm

Hi Michal,

I respond to your mail on the forum.

Is this using internal hardware SPI module in dsPIC, or it's using softwarable SPI from blockset

It use the hardware SPI peripheral.

If I want to use i.e. 6 SPI modules to communicate with 6 peripheral devices, but my PIC has only 2 modules, can I to do it?

Yes, Only one module is necessary to communicate with 6 peripherals devices :
the three lines SCK, SDI and SDO will be common to all devices (this is the bus).
Each peripheral will also be connected to a fourth line : Chip Select. Peripheral devices with their Chip Select line disable should be in high impedance on the bus.

The illustration shows a typical use of the SPI block.
SPI_example.png
Read 2 SPI data from One Chip
SPI_example.png (6.5 KiB) Viewed 1412 times

Note the ordering connection between blocks to force the execution order.
Digital Write is used to drive the Chip Select line.
On, this example, we read two different data from the same chip (There is only one Chip Select line: E5)
Also, note the Nop blocks that allow slowing down the start of transmission on the bus after the Chip Select line is enable. This gives time for the Chip Select line to be stable. It is safe to place the SPI logic inside a subsystem with the subsystem parameters "Treat as atomic" checked. This will force all blocks to be executed without being mixed up by execution of others blocks from the model.

Lubin

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