I am using calculus time step to try to understand what load the processor is running at. What I have found is odd.
For a simulation time configured as 1E5, I varied the sample time of an ADC block that was just converted to binary and the LSB used to drive a digital line (model attached). The outputs of the calculus time step block are T and PR1. My PIC is configured at 40MIPS. I was sampling Calculus Time Step at 100Hz and using the TX_Labview_Matlab block for serial output. My results were:
ADC sampling at 10Hz PR1=400 T=106
ADC sampling at 1000Hz PR1=400 T=104
ADC sampling at 100000Hz PR1=400 T=82
The PR1 of 400 makes sense (40M/100K=400), but I would have expected that at 100kHz the T would be MUCH MUCH greater than at 10Hz. What am I missing? Is my processor really running at 25% load at 10Hz ADC sampling and 20% load at 100,000Hz?
Confused about calculus time step

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Re: Confused about calculus time step
Forgot to attach the model. Here it is. I am using Matlab r2009b.
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 calculus_timestep_test.mdl
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Re: Confused about calculus time step
Hey Corey,
Thanks for this interresting question.
These measurement are absolutly normal.
 You changed the sampling time of the ADC inside the ADC block.
 The model timestep was fixed at 100Khz (T = 10us) (quite high). PR1 = 400 : 400 instructions are executed within 10us
 The 20% or 25% load you measured here correspond to the background task : an average of (106 ,104 ,84) instructions are executed within each 10us timestep. (background code is simpler when blocks are sampled at the same sampling time as the model, explaining the unexpected load decrease while ADC is sampled here at 100kHz.)
The ADC block works with interruptions. The channel AN_4 is sampled "continuously" (via interruption, at 10.1us here) what ever is the ADC block output rate. The ADC block output undersample these value at the ADC block sampling time. Thus, the model load does not depend on the ADC sampling rate.
What you may want to do is :
to set the ADC sampling rate to 1 and change it through the model timestep. That would modify PR1 while T remains constant (around 100). The dsPIC % load will decrease as sampling rate decrease.
On the experience you made, the very small change you want to see is the time for copying of the LSB of the AN_4 to the A1 digital output (following code).
More precisely, you are not measuring the time of part of code in your two first experiences:
The Time Step block output the is the time step of the previous model time step ! (The current time step which is not finished and cannot be measured yet)
When the model is sampled at 100kHz and ADC to Digital output calculation is executed at 1kHz (100x slower), it may be interresting to compare one step where calculation is done (1kHz) and one step where nothing is done (99 of the steps within 10us)!
to do so :
 configure ADC block sampling time to .001 (1kHz)
 place one Time Step blocks with sampling time set to : [.001 0]
 place another Time Step blocks with sampling time set to [0.001 .00001]
(after these two Time Step blocks, you will have to place a transition rate converter to send both values to the Tx_Matlab_Labview block.)
==> The first Time Step block provides the measure for the time step prior to the ADC to A1 calculations
==> The second Time Step block provides the measure for the time step with ADC to A1 calculations
sampling time parameters composed of two figures : [Samplint time  Offset]
Let me know if you need any precisions
It would be interresting to get your feedback or results you received.
Lubin
Thanks for this interresting question.
These measurement are absolutly normal.
 You changed the sampling time of the ADC inside the ADC block.
 The model timestep was fixed at 100Khz (T = 10us) (quite high). PR1 = 400 : 400 instructions are executed within 10us
 The 20% or 25% load you measured here correspond to the background task : an average of (106 ,104 ,84) instructions are executed within each 10us timestep. (background code is simpler when blocks are sampled at the same sampling time as the model, explaining the unexpected load decrease while ADC is sampled here at 100kHz.)
The ADC block works with interruptions. The channel AN_4 is sampled "continuously" (via interruption, at 10.1us here) what ever is the ADC block output rate. The ADC block output undersample these value at the ADC block sampling time. Thus, the model load does not depend on the ADC sampling rate.
What you may want to do is :
to set the ADC sampling rate to 1 and change it through the model timestep. That would modify PR1 while T remains constant (around 100). The dsPIC % load will decrease as sampling rate decrease.
On the experience you made, the very small change you want to see is the time for copying of the LSB of the AN_4 to the A1 digital output (following code).
Code: Select all
98 /* SFunction "ADC" Block: <Root>/ADC Input */
99 calculus_timestep_test_B.ADCInput = ADC1BUF0;
100
101 /* DataTypeConversion: '<Root>/Data Type Conversion' incorporates:
102 * SFunction (sfix_bitop): '<Root>/Bitwise Operator'
103 */
104 calculus_timestep_test_B.DataTypeConversion =
105 ((calculus_timestep_test_B.ADCInput &
106 calculus_timestep_test_P.BitwiseOperator_BitMask) != 0U);
107
108 /* SFunction "dsPIC_Digital_OutputWrite" Block: <Root>/Digital Output Write1 */
109 LATAbits.LATA1 = calculus_timestep_test_B.DataTypeConversion;
110 }
The Time Step block output the is the time step of the previous model time step ! (The current time step which is not finished and cannot be measured yet)
When the model is sampled at 100kHz and ADC to Digital output calculation is executed at 1kHz (100x slower), it may be interresting to compare one step where calculation is done (1kHz) and one step where nothing is done (99 of the steps within 10us)!
to do so :
 configure ADC block sampling time to .001 (1kHz)
 place one Time Step blocks with sampling time set to : [.001 0]
 place another Time Step blocks with sampling time set to [0.001 .00001]
(after these two Time Step blocks, you will have to place a transition rate converter to send both values to the Tx_Matlab_Labview block.)
==> The first Time Step block provides the measure for the time step prior to the ADC to A1 calculations
==> The second Time Step block provides the measure for the time step with ADC to A1 calculations
sampling time parameters composed of two figures : [Samplint time  Offset]
Let me know if you need any precisions
It would be interresting to get your feedback or results you received.
Lubin
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