My C30 code does working now for the DAc peripherical on dspic33fj64gp802.
Code: Select all
#include "p33FJ64GP802.h"
#include "dsp.h"
long i,j,k;
long mydataright,mydataleft;
int const sinus[60]={10,500,500,150,10,500,10,10,150,500,
500,10,350,500,10,10,10,350,500,500,
10,10,10,10,150,150,150,150,150,150,
350,350,350,350,500,500,500,500,500,500,
500,150,350,10,10,350,150,500,10,150,
150,350,10,500,500,10,150,350,10,10};
int const cosinus[60]={150,10,350,500,150,10,10,350,500,500,
10,150,10,500,10,350,10,500,10,150,
10,150,350,500,10,150,350,500,500,150,
500,350,150,10,10,150,350,500,10,10,
10,10,10,10,150,150,150,150,10,500,
500,500,500,500,350,350,350,10,150};
void __attribute__((interrupt,no_auto_psv))_DAC1RInterrupt(void);
void __attribute__((interrupt,no_auto_psv))_DAC1LInterrupt(void);
void initDAC();
void __attribute__((interrupt,no_auto_psv)) _DAC1RInterrupt(void)
{
IFS4bits.DAC1RIF = 0; /* Clear Right Channel Interrupt Flag */
DAC1RDAT = mydataright; /* User Code to Write to FIFO Goes Here */
}
void __attribute__((interrupt, no_auto_psv)) _DAC1LInterrupt(void)
{
IFS4bits.DAC1LIF = 0; /* Clear Right Channel Interrupt Flag */
DAC1LDAT = mydataleft; /* User Code to Write to FIFO Goes Here */
}
void initDAC()
{
ACLKCONbits.SELACLK=0;
ACLKCONbits.AOSCMD=0;
ACLKCONbits.ASRCSEL=0;
ACLKCONbits.APSTSCLR=7; //divide clock by 8
DAC1STATbits.ROEN = 1; /* Right Channel DAC Output Enabled */
DAC1STATbits.LOEN = 1; /* Right Channel DAC Output Enabled */
DAC1STATbits.RITYPE = 0; /* Right Channel Interrupt if FIFO is not Full */
DAC1STATbits.LITYPE = 0; /* Right Channel Interrupt if FIFO is not Full */
DAC1CONbits.AMPON = 0; /* Amplifier Disabled During Sleep and Idle Modes */
DAC1CONbits.DACFDIV = 5; /* Divide Clock by 100 (Assumes Clock is 25.6MHz) */
//PLLCLK=80MHZ ; ACLK=10MHz ; DACCLK=100kHz
DAC1CONbits.FORM = 0; /* Data Format is unsigned integer */
DAC1DFLT = 0x8000; /* Default value set to Midpoint when FORM = 0 */
IFS4bits.DAC1RIF = 0; /* Clear Right Channel Interrupt Flag */
IFS4bits.DAC1LIF = 0; /* Clear Right Channel Interrupt Flag */
IEC4bits.DAC1RIE = 1; /* Right Channel Interrupt Enabled */
IEC4bits.DAC1LIE = 1; /* Right Channel Interrupt Enabled */
DAC1CONbits.DACEN = 1; /* DAC1 Module Enabled */
}
long writeDACdataR(void)
{
mydataright=128*sinus[i];
mydataleft=128*cosinus[i];
}
// Internal FRC Oscillator
_FOSCSEL(FNOSC_FRC); // FRC Oscillator
_FOSC(FCKSM_CSECMD & OSCIOFNC_ON & POSCMD_NONE);
//_FOSC(FCKSM_CSECMD);
_FWDT(FWDTEN_OFF); // Watchdog Timer Enabled/disabled by user software
// (LPRC can be disabled by clearing SWDTEN bit in RCON register
int main(void)
{
/* Configure Oscillator to operate the device at 40Mhz
Fosc= Fin*M/(N1*N2), Fcy=Fosc/2
Fosc= 7.37*M*43/(2*2)=80Mhz for 7.37M internal FRC */
PLLFBD=42; /* M=43 */
CLKDIVbits.PLLPOST=0; /* N1=2 */
CLKDIVbits.PLLPRE=0; /* N2=2 */
OSCTUN=23; /* Tune FRC oscillator, if FRC is used */
/* Disable Watch Dog Timer */
RCONbits.SWDTEN=0;
/* Clock switch to incorporate PLL*/
__builtin_write_OSCCONH(0x01); // Initiate Clock Switch to FRC
// Oscillator with PLL (NOSC=0b001)
__builtin_write_OSCCONL(0x01); // Start clock switching
while (OSCCONbits.COSC != 0b001); // Wait for Clock switch to occur
/* Wait for PLL to lock */
while(OSCCONbits.LOCK!=1);
//OSCCONbits.LPOSCEN=0;
CLKDIVbits.DOZE=0b000;
CLKDIVbits.FRCDIV=0b000;
// Initiate Clock Switch to FRC oscillator with PLL (NOSC=0b001)
// Wait for Clock switch to occur
while (OSCCONbits.COSC != 0b001);
initDAC();
i=1;
k=0;
for(;;)
{
while (j<400)
{
j=j+1;
}
j=0;
i=i+1;
writeDACdataR();
if (i>60)
{
i=0;
}
}
}