Hi Lubin,
Thanks for your patient explanation.
I will add some detailed explanation for OC(HW).
Quan
Search found 3 matches
- Fri Jul 31, 2009 3:47 am
- Forum: General Remark and Questions
- Topic: Duty cycle of OC(HW)
- Replies: 4
- Views: 13131
- Thu Jul 30, 2009 2:46 pm
- Forum: General Remark and Questions
- Topic: Duty cycle of OC(HW)
- Replies: 4
- Views: 13131
Re: Duty cycle of OC(HW)
Hi Lubin,
Sorry for bothering you again.
I have read the block page many times, still I cannot get what I want.
Attached is a graph got from the example of Hyper Sampling.
Could you explain how the duty cycle is decided and why there is a "+" between the set and reset inputs?
Thanks very much.
Quan
Sorry for bothering you again.
I have read the block page many times, still I cannot get what I want.
Attached is a graph got from the example of Hyper Sampling.
Could you explain how the duty cycle is decided and why there is a "+" between the set and reset inputs?
Thanks very much.
Quan
- Thu Jul 30, 2009 4:50 am
- Forum: General Remark and Questions
- Topic: Duty cycle of OC(HW)
- Replies: 4
- Views: 13131
Duty cycle of OC(HW)
Hi Lubin,
I am making a sampling using the OC(HW) and ADC.
In the dialog of OC(HW), we can set the period for the PWM output.
However, I am not clear about setting the duty cycle.
Could you explain exactly what the set and reset mean in the block?
Thanks in advance.
Quan
I am making a sampling using the OC(HW) and ADC.
In the dialog of OC(HW), we can set the period for the PWM output.
However, I am not clear about setting the duty cycle.
Could you explain exactly what the set and reset mean in the block?
Thanks in advance.
Quan