Model { Name "uC_Stateflow_after" Version 7.7 MdlSubVersion 0 GraphicalInterface { NumRootInports 0 NumRootOutports 0 ParameterArgumentNames "" ComputedModelVersion "1.368" NumModelReferences 0 NumTestPointedSignals 0 } SavedCharacterEncoding "windows-1252" SaveDefaultBlockParams on ScopeRefreshTime 0.035000 OverrideScopeRefreshTime on DisableAllScopes off DataTypeOverride "UseLocalSettings" DataTypeOverrideAppliesTo "AllNumericTypes" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" MaxMDLFileLineLength 120 InitFcn "St=0.01;\nidleSPL=170;\nidleSPR=170;\ndeltaIdle=80;" Created "Thu Jan 31 09:48:18 2013" Creator "AKS1DY" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "pcadmin" ModifiedDateFormat "%" LastModifiedDate "Thu Dec 19 10:45:02 2013" RTWModifiedTimeStamp 309349958 ModelVersionFormat "1.%" ConfigurationManager "None" SampleTimeColors on SampleTimeAnnotations on LibraryLinkDisplay "none" WideLines off ShowLineDimensions on ShowPortDataTypes on ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ShowTestPointIcons on ShowSignalResolutionIcons on ShowViewerIcons on SortedOrder off ExecutionContextIcon off ShowLinearizationAnnotations on BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off SimulationMode "normal" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off Object { $PropName "DataLoggingOverride" $ObjectID 1 $ClassName "Simulink.SimulationData.ModelLoggingInfo" model_ "uC_Stateflow_after" overrideMode_ [0.0] Array { Type "Cell" Dimension 1 Cell "uC_Stateflow_after" PropName "logAsSpecifiedByModels_" } Array { Type "Cell" Dimension 1 Cell [] PropName "logAsSpecifiedByModelsSSIDs_" } } RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on CovForceBlockReductionOff on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off CovReportOnPause on CovModelRefEnable "Off" CovExternalEMLEnable off ExtModeBatchMode off ExtModeEnableFloating on ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigDurationFloating "auto" ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse on ShowModelReferenceBlockVersion off ShowModelReferenceBlockIO off Array { Type "Handle" Dimension 1 Simulink.ConfigSet { $ObjectID 2 Version "1.11.0" Array { Type "Handle" Dimension 8 Simulink.SolverCC { $ObjectID 3 Version "1.11.0" StartTime "0" StopTime "10.0" AbsTol "auto" FixedStep "0.001" InitialStep "auto" MaxNumMinSteps "-1" MaxOrder 5 ZcThreshold "auto" ConsecutiveZCsStepRelTol "10*128*eps" MaxConsecutiveZCs "1000" ExtrapolationOrder 4 NumberNewtonIterations 1 MaxStep "auto" MinStep "auto" MaxConsecutiveMinStep "1" RelTol "1e-3" SolverMode "SingleTasking" ConcurrentTasks off Solver "FixedStepDiscrete" SolverName "FixedStepDiscrete" SolverJacobianMethodControl "auto" ShapePreserveControl "DisableAll" ZeroCrossControl "UseLocalSettings" ZeroCrossAlgorithm "Nonadaptive" AlgebraicLoopSolver "TrustRegion" SolverResetMethod "Fast" PositivePriorityOrder off AutoInsertRateTranBlk off SampleTimeConstraint "Unconstrained" InsertRTBMode "Whenever possible" } Simulink.DataIOCC { $ObjectID 4 Version "1.11.0" Decimation "1" ExternalInput "[t, u]" FinalStateName "xFinal" InitialState "xInitial" LimitDataPoints on MaxDataPoints "1000" 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LocalBlockOutputs on RollThreshold 5 SystemCodeInlineAuto off StateBitsets off DataBitsets off UseTempVars off ZeroExternalMemoryAtStartup on ZeroInternalMemoryAtStartup on InitFltsAndDblsToZero off NoFixptDivByZeroProtection off EfficientFloat2IntCast off EfficientMapNaN2IntZero on OptimizeModelRefInitCode on LifeSpan "1" MaxStackSize "Inherit from target" BufferReusableBoundary on SimCompilerOptimization "Off" AccelVerboseBuild off AccelParallelForEachSubsystem on } Simulink.DebuggingCC { $ObjectID 6 Version "1.11.0" RTPrefix "error" ConsistencyChecking "none" ArrayBoundsChecking "none" SignalInfNanChecking "none" SignalRangeChecking "none" ReadBeforeWriteMsg "UseLocalSettings" WriteAfterWriteMsg "UseLocalSettings" WriteAfterReadMsg "UseLocalSettings" AlgebraicLoopMsg "warning" ArtificialAlgebraicLoopMsg "warning" SaveWithDisabledLinksMsg "warning" SaveWithParameterizedLinksMsg "warning" CheckSSInitialOutputMsg on UnderspecifiedInitializationDetection "Classic" MergeDetectMultiDrivingBlocksExec "none" CheckExecutionContextPreStartOutputMsg off CheckExecutionContextRuntimeOutputMsg off SignalResolutionControl "UseLocalSettings" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" TimeAdjustmentMsg "none" MaxConsecutiveZCsMsg "error" MaskedZcDiagnostic "warning" IgnoredZcDiagnostic "warning" SolverPrmCheckMsg "warning" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskDSMMsg "error" MultiTaskCondExecSysMsg "error" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" TasksWithSamePriorityMsg "warning" SigSpecEnsureSampleTimeMsg "warning" CheckMatrixSingularityMsg "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterUnderflowMsg "none" ParameterPrecisionLossMsg "warning" ParameterTunabilityLossMsg "warning" FixptConstUnderflowMsg "none" FixptConstOverflowMsg "none" FixptConstPrecisionLossMsg "none" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" FcnCallInpInsideContextMsg "Use local settings" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SFcnCompatibilityMsg "none" UniqueDataStoreMsg "none" BusObjectLabelMismatch "warning" RootOutportRequireBusObject "warning" AssertControl "UseLocalSettings" EnableOverflowDetection off ModelReferenceIOMsg "none" ModelReferenceMultiInstanceNormalModeStructChecksumCheck "error" ModelReferenceVersionMismatchMessage "none" ModelReferenceIOMismatchMessage "none" ModelReferenceCSMismatchMessage "none" UnknownTsInhSupMsg "warning" ModelReferenceDataLoggingMessage "warning" ModelReferenceSymbolNameMessage "warning" ModelReferenceExtraNoncontSigs "error" StateNameClashWarn "warning" SimStateInterfaceChecksumMismatchMsg "warning" SimStateOlderReleaseMsg "error" InitInArrayFormatMsg "warning" StrictBusMsg "ErrorLevel1" BusNameAdapt "WarnAndRepair" NonBusSignalsTreatedAsBus "none" LoggingUnavailableSignals "error" BlockIODiagnostic "none" SFUnusedDataAndEventsDiag "warning" SFUnexpectedBacktrackingDiag "warning" SFInvalidInputDataAccessInChartInitDiag "warning" SFNoUnconditionalDefaultTransitionDiag "warning" SFTransitionOutsideNaturalParentDiag "warning" } Simulink.HardwareCC { $ObjectID 7 Version "1.11.0" Array { Type "Cell" Dimension 2 Cell "ProdHWDeviceType" Cell "ProdEqTarget" PropName "DisabledProps" } ProdBitPerChar 8 ProdBitPerShort 16 ProdBitPerInt 16 ProdBitPerLong 32 ProdBitPerFloat 32 ProdBitPerDouble 64 ProdBitPerPointer 16 ProdLargestAtomicInteger "Char" ProdLargestAtomicFloat "None" ProdIntDivRoundTo "Undefined" ProdEndianess "LittleEndian" ProdWordSize 16 ProdShiftRightIntArith on ProdHWDeviceType "16-bit Generic" TargetBitPerChar 8 TargetBitPerShort 16 TargetBitPerInt 32 TargetBitPerLong 32 TargetBitPerFloat 32 TargetBitPerDouble 64 TargetBitPerPointer 32 TargetLargestAtomicInteger "Char" TargetLargestAtomicFloat "None" TargetShiftRightIntArith on TargetIntDivRoundTo "Undefined" TargetEndianess "Unspecified" TargetWordSize 32 TargetTypeEmulationWarnSuppressLevel 0 TargetPreprocMaxBitsSint 32 TargetPreprocMaxBitsUint 32 TargetHWDeviceType "Specified" TargetUnknown off ProdEqTarget on } Simulink.ModelReferenceCC { $ObjectID 8 Version "1.11.0" UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange" CheckModelReferenceTargetMessage "error" EnableParallelModelReferenceBuilds off ParallelModelReferenceErrorOnInvalidPool on ParallelModelReferenceMATLABWorkerInit "None" ModelReferenceNumInstancesAllowed "Multi" PropagateVarSize "Infer from blocks in model" ModelReferencePassRootInputsByReference on ModelReferenceMinAlgLoopOccurrences off PropagateSignalLabelsOutOfModel off SupportModelReferenceSimTargetCustomCode off } Simulink.SFSimCC { $ObjectID 9 Version "1.11.0" SFSimEnableDebug on SFSimOverflowDetection on SFSimEcho on SimBlas on SimCtrlC on SimExtrinsic on SimIntegrity on SimUseLocalCustomCode off SimParseCustomCode on SimBuildMode "sf_incremental_build" } Simulink.RTWCC { $BackupClass "Simulink.RTWCC" $ObjectID 10 Version "1.11.0" Array { Type "Cell" Dimension 1 Cell "TargetLang" PropName "DisabledProps" } SystemTargetFile "dspic.tlc" GenCodeOnly off MakeCommand "make_CreateMPLAB" GenerateMakefile on TemplateMakefile "dspic_pic30_gcc.tmf" PostCodeGenCommand "dsPIC_Compile()" Description "Embedded Target for Microchip dsPIC (real-time)" GenerateReport off SaveLog off RTWVerbose on RetainRTWFile off ProfileTLC off TLCDebug off TLCCoverage off TLCAssert off ProcessScriptMode "Default" ConfigurationMode "Optimized" ProcessScript "dspic_make_rtw_hook" ConfigAtBuild off RTWUseLocalCustomCode off RTWUseSimCustomCode off IncludeHyperlinkInReport off LaunchReport off TargetLang "C" IncludeBusHierarchyInRTWFileBlockHierarchyMap off IncludeERTFirstTime off GenerateTraceInfo off GenerateTraceReport off GenerateTraceReportSl off GenerateTraceReportSf off GenerateTraceReportEml off GenerateCodeInfo off GenerateSLWebview off GenerateCodeMetricsReport off RTWCompilerOptimization "Off" CheckMdlBeforeBuild "Off" CustomRebuildMode "OnUpdate" Array { Type "Handle" Dimension 2 Simulink.CodeAppCC { $ObjectID 11 Version "1.11.0" ForceParamTrailComments off GenerateComments on IgnoreCustomStorageClasses off IgnoreTestpoints off IncHierarchyInIds off MaxIdLength 31 PreserveName off PreserveNameWithParent off ShowEliminatedStatement off IncAutoGenComments off SimulinkDataObjDesc off SFDataObjDesc off MATLABFcnDesc off IncDataTypeInIds off MangleLength 1 CustomSymbolStrGlobalVar "$R$N$M" CustomSymbolStrType "$N$R$M" CustomSymbolStrField "$N$M" CustomSymbolStrFcn "$R$N$M$F" CustomSymbolStrFcnArg "rt$I$N$M" CustomSymbolStrBlkIO "rtb_$N$M" CustomSymbolStrTmpVar "$N$M" CustomSymbolStrMacro "$R$N$M" DefineNamingRule "None" ParamNamingRule "None" SignalNamingRule "None" InsertBlockDesc off InsertPolySpaceComments off SimulinkBlockComments on MATLABSourceComments off EnableCustomComments off InlinedPrmAccess "Literals" ReqsInCode off UseSimReservedNames off } Simulink.STFCustomTargetCC { $BackupClass "Simulink.TargetCC" $ObjectID 12 Version "1.11.0" Array { Type "Cell" Dimension 6 Cell "GenerateSampleERTMain" Cell "MatFileLogging" Cell "SupportNonInlinedSFcns" Cell "UtilityFuncGeneration" Cell "IncludeMdlTerminateFcn" Cell "ModelReferenceCompliant" PropName "DisabledProps" } TargetFcnLib "ansi_tfl_table_tmw.mat" TargetLibSuffix "" TargetPreCompLibLocation "" TargetFunctionLibrary "ANSI_C" UtilityFuncGeneration "Auto" ERTMultiwordTypeDef "System defined" FunctionExecutionProfile off CodeExecutionProfiling off ERTCodeCoverageTool "None" ERTMultiwordLength 256 MultiwordLength 2048 GenerateFullHeader on GenerateSampleERTMain off GenerateTestInterfaces off IsPILTarget off ModelReferenceCompliant on ParMdlRefBuildCompliant off CompOptLevelCompliant off IncludeMdlTerminateFcn off GeneratePreprocessorConditionals "Use local settings" CombineOutputUpdateFcns on CombineSignalStateStructs off SuppressErrorStatus on ERTFirstTimeCompliant off IncludeFileDelimiter "Auto" ERTCustomFileBanners on SupportAbsoluteTime on LogVarNameModifier "rt_" MatFileLogging off MultiInstanceERTCode off SupportNonFinite on SupportComplex on PurelyIntegerCode off SupportContinuousTime off SupportNonInlinedSFcns off SupportVariableSizeSignals off EnableShiftOperators on ParenthesesLevel "Nominal" PortableWordSizes off ModelStepFunctionPrototypeControlCompliant off CPPClassGenCompliant off AutosarCompliant off SystemTargetFile "dspic.tlc" DialogCategory 0 Array { Type "Handle" Dimension 1 Simulink.ERTTargetCC { $BackupClass "Simulink.TargetCC" $ObjectID 13 Version "1.11.0" Array { Type "Cell" Dimension 9 Cell "GenerateSampleERTMain" Cell "GenerateErtSFunction" Cell "MatFileLogging" Cell "GRTInterface" Cell "ERTCustomFileTemplate" Cell "SupportNonInlinedSFcns" Cell "UtilityFuncGeneration" Cell "IncludeMdlTerminateFcn" Cell "ModelReferenceCompliant" PropName "DisabledProps" } TargetFcnLib "ansi_tfl_table_tmw.mat" TargetLibSuffix "" TargetPreCompLibLocation "" TargetFunctionLibrary "ANSI_C" UtilityFuncGeneration "Auto" ERTMultiwordTypeDef "System defined" FunctionExecutionProfile off CodeExecutionProfiling off ERTCodeCoverageTool "None" ERTMultiwordLength 256 MultiwordLength 2048 GenerateFullHeader on GenerateSampleERTMain off GenerateTestInterfaces off IsPILTarget off ModelReferenceCompliant on ParMdlRefBuildCompliant off CompOptLevelCompliant off IncludeMdlTerminateFcn off GeneratePreprocessorConditionals "Use local settings" CombineOutputUpdateFcns on CombineSignalStateStructs off SuppressErrorStatus on ERTFirstTimeCompliant off IncludeFileDelimiter "Auto" ERTCustomFileBanners on SupportAbsoluteTime on LogVarNameModifier "rt_" MatFileLogging off MultiInstanceERTCode off SupportNonFinite on SupportComplex on PurelyIntegerCode off SupportContinuousTime off SupportNonInlinedSFcns off SupportVariableSizeSignals off EnableShiftOperators on ParenthesesLevel "Nominal" PortableWordSizes off ModelStepFunctionPrototypeControlCompliant off CPPClassGenCompliant off AutosarCompliant off GenerateErtSFunction off CreateSILPILBlock "None" CodeExecutionProfileVariable "executionProfile" GenerateASAP2 off ExtMode off ExtModeTransport 0 ExtModeStaticAlloc off ExtModeStaticAllocSize 1000000 ExtModeTesting off ExtModeMexFile "ext_serial_win32_comm" ExtModeIntrfLevel "Level1" InlinedParameterPlacement "NonHierarchical" TargetOS "BareBoardExample" MultiInstanceErrorCode "Error" RateGroupingCode on RootIOFormat "Individual arguments" RTWCAPISignals off RTWCAPIParams off RTWCAPIStates off RTWCAPIRootIO off ERTSrcFileBannerTemplate "dsPIC_code_template.cgt" ERTHdrFileBannerTemplate "dsPIC_code_template.cgt" ERTDataSrcFileTemplate "dsPIC_code_template.cgt" ERTDataHdrFileTemplate "dsPIC_code_template.cgt" ERTCustomFileTemplate "dsPIC_main.tlc" CoverageDialogOpen "off" ModuleNamingRule "Unspecified" SignalDisplayLevel 10 ParamTuneLevel 10 GlobalDataDefinition "Auto" DataDefinitionFile "global.c" GlobalDataReference "Auto" ERTFilePackagingFormat "Modular" DataReferenceFile "global.h" GRTInterface off PreserveExpressionOrder off PreserveIfCondition off ConvertIfToSwitch off PreserveExternInFcnDecls on EnableUserReplacementTypes off Array { Type "Struct" Dimension 1 MATStruct { double "" single "" int32 "" int16 "" int8 "" uint32 "" uint16 "" uint8 "" boolean "" int "" uint "" char "" } PropName "ReplacementTypes" } MemSecPackage "--- None ---" MemSecDataConstants "Default" MemSecDataIO "Default" MemSecDataInternal "Default" MemSecDataParameters "Default" MemSecFuncInitTerm "Default" MemSecFuncExecute "Default" MemSecFuncSharedUtil "Default" } PropName "Components" } CustomProperty { DataType "string" Name "GMAKE_PLACE" Value "C:\\PROGRA~1\\MATLAB\\R2011a\\bin\\win32\\gmake" } CustomProperty { DataType "string" Name "OPTIM_GCC" Value "-mcpu=33fJ256MC710a -O3 -fschedule-insns -fschedule-insns2" } CustomProperty { DataType "string" Name "LDFLAGS" Value " -Xlinker -t -Xlinker --report-mem -Xlinker -Map=../untitled.map -Xlinker --heap=0 -Xlinker -cref" } CustomProperty { DataType "string" Name "LDPICTYPE" Value " -Xlinker --script=C:\\PROGRA~1\\MICROC~1\\mplabc30\\v3.30\\support\\dsPIC33F\\gld\\p33fJ256MC710a.gld" } CustomProperty { DataType "string" Name "LDLIBPIC" Value " C:\\PROGRA~1\\MICROC~1\\mplabc30\\v3.30\\lib\\libpic30-coff.a C:\\PROGRA~1\\MICROC~1\\mplabc30\\v3.30\\lib" "\\dsPIC33F\\libp33fJ256MC710a-coff.a C:\\PROGRA~1\\MICROC~1\\mplabc30\\v3.30\\lib\\libc-coff.a C:\\PROGRA~1\\MICROC~" "1\\mplabc30\\v3.30\\lib\\libm-coff.a" } CustomProperty { DataType "string" Name "PIC_INCLUDES" Value " -I C:\\PROGRA~1\\MICROC~1\\mplabc30\\v3.30\\include" } CustomProperty { DataType "string" Name "PIC_REF" Value "33fJ256MC710a" } CustomProperty { DataType "string" Name "GCCPATH" Value "''" } } PropName "Components" } } PropName "Components" } Name "Configuration" ExtraOptions "-aGenerateTraceInfo=0 -aIgnoreTestpoints=0 " CurrentDlgPage "Solver" ConfigPrmDlgPosition [ 308, 75, 1188, 705 ] } PropName "ConfigurationSets" } Simulink.ConfigSet { $PropName "ActiveConfigurationSet" $ObjectID 2 } BlockDefaults { ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on BlockRotation 0 BlockMirror off } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" UseDisplayTextAsClickCallback off } LineDefaults { FontName "Helvetica" FontSize 9 FontWeight "normal" FontAngle "normal" } BlockParameterDefaults { Block { BlockType BusCreator Inputs "4" DisplayOption "none" OutDataTypeStr "Inherit: auto" NonVirtualBus off } Block { BlockType Constant Value "1" VectorParams1D on SamplingMode "Sample based" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Inherit from 'Constant value'" LockScale off SampleTime "inf" FramePeriod "inf" PreserveConstantTs off } Block { BlockType DataTypeConversion OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Inherit via back propagation" LockScale off ConvertRealWorld "Real World Value (RWV)" RndMeth "Zero" SaturateOnIntegerOverflow on SampleTime "-1" } Block { BlockType Demux Outputs "4" DisplayOption "none" BusSelectionMode off } Block { BlockType Gain Gain "1" Multiplication "Element-wise(K.*u)" ParamMin "[]" ParamMax "[]" ParamDataTypeStr "Inherit: Same as input" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Same as input" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on SampleTime "-1" } Block { BlockType Inport Port "1" OutputFunctionCall off OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: auto" LockScale off BusOutputAsStruct off PortDimensions "-1" VarSizeSig "Inherit" SampleTime "-1" SignalType "auto" SamplingMode "auto" LatchByDelayingOutsideSignal off LatchInputForFeedbackSignals off Interpolate on } Block { BlockType Outport Port "1" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: auto" LockScale off BusOutputAsStruct off PortDimensions "-1" VarSizeSig "Inherit" SampleTime "-1" SignalType "auto" SamplingMode "auto" SourceOfInitialOutputValue "Dialog" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType RateTransition Integrity on Deterministic on X0 "0" OutPortSampleTimeOpt "Specify" OutPortSampleTimeMultiple "1" OutPortSampleTime "-1" } Block { BlockType S-Function FunctionName "system" SFunctionModules "''" PortCounts "[]" SFunctionDeploymentMode off } Block { BlockType SubSystem ShowPortLabels "FromPortIcon" Permissions "ReadWrite" PermitHierarchicalResolution "All" TreatAsAtomicUnit off CheckFcnCallInpInsideContextMsg off SystemSampleTime "-1" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" SimViewingDevice off DataTypeOverride "UseLocalSettings" DataTypeOverrideAppliesTo "AllNumericTypes" MinMaxOverflowLogging "UseLocalSettings" Variant off GeneratePreprocessorConditionals off } Block { BlockType Sum IconShape "rectangular" Inputs "++" CollapseMode "All dimensions" CollapseDim "1" InputSameDT on AccumDataTypeStr "Inherit: Inherit via internal rule" OutMin "[]" OutMax "[]" OutDataTypeStr "Inherit: Same as first input" LockScale off RndMeth "Floor" SaturateOnIntegerOverflow on SampleTime "-1" } Block { BlockType Terminator } } System { Name "uC_Stateflow_after" Location [7, 82, 1265, 742] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" ReportName "simulink-default.rpt" SIDHighWatermark "904" Block { BlockType Reference Name "ADC Input" SID "685" Tag "dsPIC_ADC" Ports [0, 3] Position [20, 171, 170, 339] Priority "5" LibraryVersion "3.79" SourceBlock "dsPICdrivers/Peripheral I//O/ADC Input" SourceType "dsPIC : ADC10" ADC_TYPE "12 bits" ADC_MODE "Continuous sampling & get last channel value" NbrSampleStep "1" VoltRefpopup "AVdd - AVss" OutFormatBitspopup "0000 dddd dddd dddd : Integer" InterruptPriority "6" ANCHANNELS "[1 8 9]" MaxName "ANmax = 4095" Rin "1e2" ADCS "53" SAMC "1" Temperature "25" DMAChannel "0" SampleTime "St" Status "OK | Tsmp=6.750e-007 | T/Channel=1.012e-005 | Tall=3.037e-005" SSRC "auto convert" } Block { BlockType Sum Name "Add" SID "824" Ports [2, 1] Position [285, 267, 315, 298] Inputs "+-" InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Reference Name "Configure Model \nfor dsPIC" SID "1" Ports [] Position [20, 19, 132, 75] ForegroundColor "blue" BackgroundColor "yellow" LibraryVersion "3.79" SourceBlock "dsPICdrivers/Simulink Configuration/Configure Model \nfor dsPIC" SourceType "" } Block { BlockType Constant Name "Constant" SID "842" Position [605, 458, 635, 472] Value "30000" SampleTime "St" } Block { BlockType Constant Name "Constant1" SID "854" Position [605, 257, 635, 273] Value "30000" SampleTime "St" } Block { BlockType Constant Name "Constant2" SID "855" Position [605, 308, 635, 322] Value "30000" SampleTime "St" } Block { BlockType Constant Name "Constant3" SID "859" Position [605, 358, 635, 372] Value "30000" SampleTime "St" } Block { BlockType Constant Name "Constant4" SID "861" Position [605, 408, 635, 422] Value "30000" SampleTime "St" } Block { BlockType Constant Name "Constant5" SID "865" Position [605, 508, 635, 522] Value "30000" SampleTime "St" } Block { BlockType Constant Name "Constant6" SID "866" Position [605, 558, 635, 572] Value "30000" SampleTime "St" } Block { BlockType Constant Name "Constant7" SID "868" Position [605, 618, 635, 632] Value "30000" SampleTime "St" } Block { BlockType DataTypeConversion Name "Data Type Conversion1" SID "649" Position [990, 43, 1065, 77] OutDataTypeStr "boolean" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Data Type Conversion2" SID "650" Position [990, 133, 1065, 167] OutDataTypeStr "boolean" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Data Type Conversion4" SID "642" Position [545, 43, 620, 77] OutDataTypeStr "double" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Data Type Conversion5" SID "792" Position [205, 244, 250, 266] OutDataTypeStr "double" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Data Type Conversion6" SID "793" Position [205, 299, 250, 321] OutDataTypeStr "double" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Data Type Conversion7" SID "782" Position [240, 189, 285, 211] OutDataTypeStr "double" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType Reference Name "Digital Input1" SID "644" Tag "dsPIC_Digital_Input" Ports [0, 1] Position [430, 38, 525, 82] LibraryVersion "3.79" SourceBlock "dsPICdrivers/Digital I//O/Digital Input" SourceType "" PORT "D" Pin "[2]" SampleTime "St" OrderingInOutPopup "None" } Block { BlockType Reference Name "Digital Output Write2" SID "652" Tag "dsPIC_Digital_Output" Ports [2] Position [1100, 61, 1235, 154] Priority "5" LibraryVersion "3.79" SourceBlock "dsPICdrivers/Digital I//O/Digital Output Write" SourceType "" PORT "A" Pin "[6 7]" Simultaneous on OrderingInOutPopup "None" } Block { BlockType SubSystem Name "Filtrage de Kalman2" SID "653" Ports [2, 3] Position [340, 154, 475, 326] LibraryVersion "1.32" ErrorFcn "Stateflow.Translate.translate" PermitHierarchicalResolution "ExplicitOnly" TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "Stateflow" MaskDescription "Embedded MATLAB block" MaskSelfModifiable on MaskDisplay "bgColor = Simulink.Root.ColorString2Rgb(get_param(gcbh, 'BackgroundColor')); image(imread('pr" "ivate/eml_membrane_16.png','png','BackgroundColor',bgColor(1:3)),'center'); disp([10 10 'fcn']);" MaskIconFrame on MaskIconOpaque off MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "normalized" System { Name "Filtrage de Kalman2" Location [257, 457, 812, 717] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "113" Block { BlockType Inport Name "Z" SID "653::55" Position [20, 101, 40, 119] IconDisplay "Port number" } Block { BlockType Inport Name "Voltage" SID "653::54" Position [20, 136, 40, 154] Port "2" IconDisplay "Port number" } Block { BlockType Demux Name " Demux " SID "653::15" Ports [1, 1] Position [270, 650, 320, 690] Outputs "1" } Block { BlockType S-Function Name " SFunction " SID "653::14" Tag "Stateflow S-Function uC_Stateflow_after 1" Ports [2, 4] Position [180, 227, 230, 648] FunctionName "sf_sfun" PortCounts "[2 4]" EnableBusSupport on Port { PortNumber 2 Name "Z1" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "Voltage1" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 4 Name "Z2" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Terminator Name " Terminator " SID "653::17" Position [460, 661, 480, 679] } Block { BlockType Outport Name "Z1" SID "653::64" Position [460, 101, 480, 119] IconDisplay "Port number" } Block { BlockType Outport Name "Voltage1" SID "653::85" Position [460, 136, 480, 154] Port "2" IconDisplay "Port number" } Block { BlockType Outport Name "Z2" SID "653::105" Position [460, 171, 480, 189] Port "3" IconDisplay "Port number" } Line { SrcBlock "Z" SrcPort 1 DstBlock " SFunction " DstPort 1 } Line { SrcBlock "Voltage" SrcPort 1 DstBlock " SFunction " DstPort 2 } Line { Name "Z1" Labels [0, 0; 0, 0] SrcBlock " SFunction " SrcPort 2 DstBlock "Z1" DstPort 1 } Line { Name "Voltage1" Labels [0, 0; 0, 0] SrcBlock " SFunction " SrcPort 3 DstBlock "Voltage1" DstPort 1 } Line { Name "Z2" Labels [0, 0; 0, 0] SrcBlock " SFunction " SrcPort 4 DstBlock "Z2" DstPort 1 } Line { SrcBlock " Demux " SrcPort 1 DstBlock " Terminator " DstPort 1 } Line { SrcBlock " SFunction " SrcPort 1 DstBlock " Demux " DstPort 1 } } } Block { BlockType Gain Name "Gain1" SID "839" Position [520, 275, 550, 305] Gain "10" ParamDataTypeStr "Inherit: Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Gain Name "Gain14" SID "885" Position [520, 225, 550, 255] Gain "100" ParamDataTypeStr "Inherit: Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Gain Name "Gain2" SID "856" Position [520, 135, 550, 165] Gain "10" ParamDataTypeStr "Inherit: Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Gain Name "Gain3" SID "857" Position [520, 325, 550, 355] Gain "100" ParamDataTypeStr "Inherit: Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Gain Name "Gain4" SID "874" Position [520, 475, 550, 505] Gain "1000000000000" ParamDataTypeStr "Inherit: Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Gain Name "Gain5" SID "860" Position [520, 375, 550, 405] Gain "100" ParamDataTypeStr "Inherit: Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Gain Name "Gain6" SID "873" Position [520, 585, 550, 615] Gain "10" ParamDataTypeStr "Inherit: Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Gain Name "Gain8" SID "871" Position [520, 525, 550, 555] Gain "1000000000000" ParamDataTypeStr "Inherit: Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Gain Name "Gain9" SID "875" Position [520, 425, 550, 455] Gain "1000" ParamDataTypeStr "Inherit: Inherit via internal rule" OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Reference Name "Master" SID "2" Tag "dsPIC_MASTER" Ports [] Position [149, 25, 249, 75] BackgroundColor "lightBlue" DropShadow on Priority "1" LibraryVersion "3.79" SourceBlock "dsPICdrivers/Master" SourceType "Master" TimeStepType "Free Run" picType "33fJ256MC710a" fcy "40000000" Quartz_33f "8e6" PLLActive_33f on fcyDesired_33f "40E6" tmr1 "[1 39999 0]" tmr1Info "Time Step : 0.001 ; Error : 0% PR1=39999" tmr2345 "[0 0 0 0 0 0 0 0]" tmr2345cfg "[-1 -1 -1 -1 -1 -1 -1 -1]" IOautoConf on typePort "[ 0 0 0 0 0 0 10 10 0 0 0 0 0 0 0 0 0 8 9 0 0 0 0 0" " 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0" " 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0" " 0 0 0 0 4 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0" " 0 0 0 0 ]" TRIS "[ 65343 65535 65535 65535 65535 65535 65535 ]" ADPCFG "12582916" MasterBusyPort "None" MasterOverloadPort "None" FOSC "Quartz (XT - HS)" ClockSwitchMonitor "Both disabled" TempProtection_33f "TEMP_ON" FPBOR "" PWRT "disable" MCLR "" ICD "ICS_PGD1" JTAGEN "JTAGEN_OFF" PowerSave off OverrideFcy off NewFcy "1e6" PR2345 "[65535 65535 65535 65535 65535 65535 65535 65535]" } Block { BlockType RateTransition Name "Rate Transition1" SID "901" Position [645, 39, 685, 81] OutPortSampleTime "0.01" } Block { BlockType RateTransition Name "Rate Transition2" SID "902" Position [910, 39, 950, 81] OutPortSampleTime "St" } Block { BlockType RateTransition Name "Rate Transition3" SID "903" Position [910, 129, 950, 171] OutPortSampleTime "St" } Block { BlockType RateTransition Name "Rate Transition4" SID "900" Position [645, 129, 685, 171] OutPortSampleTime "0.01" } Block { BlockType SubSystem Name "Serial Communication\nUART" SID "742" Description "Send data from microcontroleur to computer" Ports [8] Position [730, 218, 860, 612] ForegroundColor "blue" MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off System { Name "Serial Communication\nUART" Location [-11, 100, 1240, 757] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "Signal1" SID "743" Position [25, 108, 55, 122] IconDisplay "Port number" } Block { BlockType Inport Name "Signal2" SID "744" Position [25, 173, 55, 187] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "Signal3" SID "745" Position [25, 233, 55, 247] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "Signal4" SID "746" Position [25, 293, 55, 307] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "Signal5" SID "747" Position [25, 358, 55, 372] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "Signal6" SID "748" Position [25, 418, 55, 432] Port "6" IconDisplay "Port number" } Block { BlockType Inport Name "Signal7" SID "749" Position [25, 493, 55, 507] Port "7" IconDisplay "Port number" } Block { BlockType Inport Name "Signal8" SID "750" Position [25, 573, 55, 587] Port "8" IconDisplay "Port number" } Block { BlockType BusCreator Name "Bus\nCreator" SID "751" Ports [18, 1] Position [865, 248, 880, 482] ShowName off Inputs "18" DisplayOption "bar" } Block { BlockType DataTypeConversion Name "Data Type Conversion1" SID "752" Position [80, 98, 155, 132] OutDataTypeStr "uint16" RndMeth "Ceiling" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Data Type Conversion10" SID "804" Position [80, 563, 155, 597] OutDataTypeStr "uint16" RndMeth "Ceiling" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Data Type Conversion2" SID "798" Position [80, 163, 155, 197] OutDataTypeStr "uint16" RndMeth "Ceiling" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Data Type Conversion3" SID "755" Position [410, 18, 485, 52] OutDataTypeStr "uint8" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Data Type Conversion4" SID "799" Position [80, 223, 155, 257] OutDataTypeStr "uint16" RndMeth "Ceiling" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Data Type Conversion5" SID "757" Position [450, 683, 525, 717] OutDataTypeStr "uint8" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Data Type Conversion6" SID "800" Position [80, 283, 155, 317] OutDataTypeStr "uint16" RndMeth "Ceiling" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Data Type Conversion7" SID "801" Position [80, 348, 155, 382] OutDataTypeStr "uint16" RndMeth "Ceiling" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Data Type Conversion8" SID "802" Position [80, 408, 155, 442] OutDataTypeStr "uint16" RndMeth "Ceiling" SaturateOnIntegerOverflow off } Block { BlockType DataTypeConversion Name "Data Type Conversion9" SID "803" Position [80, 483, 155, 517] OutDataTypeStr "uint16" RndMeth "Ceiling" SaturateOnIntegerOverflow off } Block { BlockType Reference Name "Extract Bits" SID "762" Ports [1, 1] Position [285, 95, 365, 135] LibraryVersion "1.236" SourceBlock "simulink/Logic and Bit\nOperations/Extract Bits" SourceType "Extract Bits" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off bitsToExtract "Range of bits" numBits "8" bitIdxRange "[8 15]" outScalingMode "Treat bit field as an integer" } Block { BlockType Reference Name "Extract Bits1" SID "763" Ports [1, 1] Position [285, 150, 365, 190] LibraryVersion "1.236" SourceBlock "simulink/Logic and Bit\nOperations/Extract Bits" SourceType "Extract Bits" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off bitsToExtract "Lower half" numBits "8" bitIdxRange "[0 7]" outScalingMode "Preserve fixed-point scaling" } Block { BlockType Reference Name "Extract Bits10" SID "764" Ports [1, 1] Position [430, 475, 510, 515] LibraryVersion "1.236" SourceBlock "simulink/Logic and Bit\nOperations/Extract Bits" SourceType "Extract Bits" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off bitsToExtract "Lower half" numBits "8" bitIdxRange "[0 7]" outScalingMode "Preserve fixed-point scaling" } Block { BlockType Reference Name "Extract Bits11" SID "765" Ports [1, 1] Position [430, 420, 510, 460] LibraryVersion "1.236" SourceBlock "simulink/Logic and Bit\nOperations/Extract Bits" SourceType "Extract Bits" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off bitsToExtract "Range of bits" numBits "8" bitIdxRange "[8 15]" outScalingMode "Treat bit field as an integer" } Block { BlockType Reference Name "Extract Bits12" SID "766" Ports [1, 1] Position [285, 505, 365, 545] LibraryVersion "1.236" SourceBlock "simulink/Logic and Bit\nOperations/Extract Bits" SourceType "Extract Bits" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off bitsToExtract "Range of bits" numBits "8" bitIdxRange "[8 15]" outScalingMode "Treat bit field as an integer" } Block { BlockType Reference Name "Extract Bits13" SID "767" Ports [1, 1] Position [285, 560, 365, 600] LibraryVersion "1.236" SourceBlock "simulink/Logic and Bit\nOperations/Extract Bits" SourceType "Extract Bits" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off bitsToExtract "Lower half" numBits "8" bitIdxRange "[0 7]" outScalingMode "Preserve fixed-point scaling" } Block { BlockType Reference Name "Extract Bits14" SID "768" Ports [1, 1] Position [430, 550, 510, 590] LibraryVersion "1.236" SourceBlock "simulink/Logic and Bit\nOperations/Extract Bits" SourceType "Extract Bits" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off bitsToExtract "Range of bits" numBits "8" bitIdxRange "[8 15]" outScalingMode "Treat bit field as an integer" } Block { BlockType Reference Name "Extract Bits15" SID "769" Ports [1, 1] Position [430, 605, 510, 645] LibraryVersion "1.236" SourceBlock "simulink/Logic and Bit\nOperations/Extract Bits" SourceType "Extract Bits" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off bitsToExtract "Lower half" numBits "8" bitIdxRange "[0 7]" outScalingMode "Preserve fixed-point scaling" } Block { BlockType Reference Name "Extract Bits2" SID "770" Ports [1, 1] Position [420, 200, 500, 240] LibraryVersion "1.236" SourceBlock "simulink/Logic and Bit\nOperations/Extract Bits" SourceType "Extract Bits" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off bitsToExtract "Lower half" numBits "8" bitIdxRange "[0 7]" outScalingMode "Preserve fixed-point scaling" } Block { BlockType Reference Name "Extract Bits3" SID "771" Ports [1, 1] Position [420, 140, 500, 180] LibraryVersion "1.236" SourceBlock "simulink/Logic and Bit\nOperations/Extract Bits" SourceType "Extract Bits" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off bitsToExtract "Range of bits" numBits "8" bitIdxRange "[8 15]" outScalingMode "Treat bit field as an integer" } Block { BlockType Reference Name "Extract Bits4" SID "772" Ports [1, 1] Position [285, 300, 365, 340] LibraryVersion "1.236" SourceBlock "simulink/Logic and Bit\nOperations/Extract Bits" SourceType "Extract Bits" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off bitsToExtract "Lower half" numBits "8" bitIdxRange "[0 7]" outScalingMode "Preserve fixed-point scaling" } Block { BlockType Reference Name "Extract Bits5" SID "773" Ports [1, 1] Position [285, 240, 365, 280] LibraryVersion "1.236" SourceBlock "simulink/Logic and Bit\nOperations/Extract Bits" SourceType "Extract Bits" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off bitsToExtract "Range of bits" numBits "8" bitIdxRange "[8 15]" outScalingMode "Treat bit field as an integer" } Block { BlockType Reference Name "Extract Bits6" SID "774" Ports [1, 1] Position [420, 340, 500, 380] LibraryVersion "1.236" SourceBlock "simulink/Logic and Bit\nOperations/Extract Bits" SourceType "Extract Bits" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off bitsToExtract "Lower half" numBits "8" bitIdxRange "[0 7]" outScalingMode "Preserve fixed-point scaling" } Block { BlockType Reference Name "Extract Bits7" SID "775" Ports [1, 1] Position [420, 280, 500, 320] LibraryVersion "1.236" SourceBlock "simulink/Logic and Bit\nOperations/Extract Bits" SourceType "Extract Bits" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off bitsToExtract "Range of bits" numBits "8" bitIdxRange "[8 15]" outScalingMode "Treat bit field as an integer" } Block { BlockType Reference Name "Extract Bits8" SID "776" Ports [1, 1] Position [285, 370, 365, 410] LibraryVersion "1.236" SourceBlock "simulink/Logic and Bit\nOperations/Extract Bits" SourceType "Extract Bits" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off bitsToExtract "Range of bits" numBits "8" bitIdxRange "[8 15]" outScalingMode "Treat bit field as an integer" } Block { BlockType Reference Name "Extract Bits9" SID "777" Ports [1, 1] Position [285, 425, 365, 465] LibraryVersion "1.236" SourceBlock "simulink/Logic and Bit\nOperations/Extract Bits" SourceType "Extract Bits" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off bitsToExtract "Lower half" numBits "8" bitIdxRange "[0 7]" outScalingMode "Preserve fixed-point scaling" } Block { BlockType Reference Name "Repeating\nSequence\nStair" SID "778" Ports [0, 1] Position [345, 20, 375, 50] LibraryVersion "1.236" SourceBlock "simulink/Sources/Repeating\nSequence\nStair" SourceType "Repeating Sequence Stair" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off OutValues "[2 4 1].'" tsamp "-1" OutMin "[]" OutMax "[]" OutDataTypeStr "double" OutputDataTypeScalingMode "double" OutDataType "fixdt(0,8)" ConRadixGroup "Best Precision: Vector-wise" OutScaling "2^-12" LockScale off } Block { BlockType Reference Name "Repeating\nSequence\nStair1" SID "779" Ports [0, 1] Position [385, 685, 415, 715] LibraryVersion "1.236" SourceBlock "simulink/Sources/Repeating\nSequence\nStair" SourceType "Repeating Sequence Stair" ShowPortLabels "FromPortIcon" SystemSampleTime "-1" FunctionWithSeparateData off RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" GeneratePreprocessorConditionals off OutValues "[3 3 3].'" tsamp "-1" OutMin "[]" OutMax "[]" OutDataTypeStr "double" OutputDataTypeScalingMode "double" OutDataType "fixdt(0,8)" ConRadixGroup "Best Precision: Vector-wise" OutScaling "2^-12" LockScale off } Block { BlockType Reference Name "Tx Output1" SID "780" Tag "dsPIC_TX" Ports [1] Position [915, 348, 985, 382] Priority "5" LibraryVersion "3.79" SourceBlock "dsPICdrivers/Serial PORT/Tx Output" SourceType "Serial Transmition" UART "2" OrderingInOutPopup "None" } Line { SrcBlock "Data Type Conversion1" SrcPort 1 Points [70, 0] Branch { DstBlock "Extract Bits" DstPort 1 } Branch { Points [0, 55] DstBlock "Extract Bits1" DstPort 1 } } Line { SrcBlock "Bus\nCreator" SrcPort 1 DstBlock "Tx Output1" DstPort 1 } Line { SrcBlock "Extract Bits" SrcPort 1 Points [10, 0; 0, -15; 235, 0; 0, 190] DstBlock "Bus\nCreator" DstPort 2 } Line { SrcBlock "Extract Bits1" SrcPort 1 Points [10, 0; 0, -45; 220, 0; 0, 175] DstBlock "Bus\nCreator" DstPort 3 } Line { SrcBlock "Repeating\nSequence\nStair" SrcPort 1 DstBlock "Data Type Conversion3" DstPort 1 } Line { SrcBlock "Data Type Conversion3" SrcPort 1 Points [140, 0; 0, 245] DstBlock "Bus\nCreator" DstPort 1 } Line { SrcBlock "Repeating\nSequence\nStair1" SrcPort 1 DstBlock "Data Type Conversion5" DstPort 1 } Line { SrcBlock "Data Type Conversion5" SrcPort 1 Points [125, 0; 0, -250] DstBlock "Bus\nCreator" DstPort 18 } Line { SrcBlock "Data Type Conversion2" SrcPort 1 Points [40, 0; 0, 40; 195, 0] Branch { Points [0, -60] DstBlock "Extract Bits3" DstPort 1 } Branch { DstBlock "Extract Bits2" DstPort 1 } } Line { SrcBlock "Data Type Conversion4" SrcPort 1 Points [40, 0; 0, 50; 20, 0] Branch { Points [0, -30] DstBlock "Extract Bits5" DstPort 1 } Branch { Points [0, 30] DstBlock "Extract Bits4" DstPort 1 } } Line { SrcBlock "Extract Bits5" SrcPort 1 Points [185, 0; 0, 70] DstBlock "Bus\nCreator" DstPort 6 } Line { SrcBlock "Extract Bits4" SrcPort 1 Points [10, 0; 0, -50; 160, 0; 0, 70] DstBlock "Bus\nCreator" DstPort 7 } Line { SrcBlock "Extract Bits3" SrcPort 1 Points [80, 0; 0, 150] DstBlock "Bus\nCreator" DstPort 4 } Line { SrcBlock "Extract Bits2" SrcPort 1 Points [65, 0; 0, 100] DstBlock "Bus\nCreator" DstPort 5 } Line { SrcBlock "Extract Bits7" SrcPort 1 Points [20, 0; 0, 50] DstBlock "Bus\nCreator" DstPort 8 } Line { SrcBlock "Extract Bits6" SrcPort 1 DstBlock "Bus\nCreator" DstPort 9 } Line { SrcBlock "Data Type Conversion6" SrcPort 1 Points [30, 0; 0, 40; 80, 0; 0, 20; 120, 0] Branch { Points [0, -60] DstBlock "Extract Bits7" DstPort 1 } Branch { DstBlock "Extract Bits6" DstPort 1 } } Line { SrcBlock "Data Type Conversion7" SrcPort 1 Points [90, 0; 0, 25] Branch { DstBlock "Extract Bits8" DstPort 1 } Branch { Points [0, 55] DstBlock "Extract Bits9" DstPort 1 } } Line { SrcBlock "Extract Bits8" SrcPort 1 Points [35, 0; 0, 5; 130, 0; 0, -25] DstBlock "Bus\nCreator" DstPort 10 } Line { SrcBlock "Extract Bits9" SrcPort 1 Points [25, 0; 0, -40; 150, 0; 0, -25] DstBlock "Bus\nCreator" DstPort 11 } Line { SrcBlock "Data Type Conversion8" SrcPort 1 Points [70, 0; 0, 70; 185, 0] Branch { Points [-10, 0; 0, -55] DstBlock "Extract Bits11" DstPort 1 } Branch { DstBlock "Extract Bits10" DstPort 1 } } Line { SrcBlock "Extract Bits11" SrcPort 1 Points [50, 0; 0, -50] DstBlock "Bus\nCreator" DstPort 12 } Line { SrcBlock "Extract Bits10" SrcPort 1 Points [65, 0; 0, -95] DstBlock "Bus\nCreator" DstPort 13 } Line { SrcBlock "Data Type Conversion9" SrcPort 1 Points [55, 0; 0, 25] Branch { DstBlock "Extract Bits12" DstPort 1 } Branch { Points [0, 55] DstBlock "Extract Bits13" DstPort 1 } } Line { SrcBlock "Extract Bits12" SrcPort 1 Points [45, 0; 0, 10; 180, 0; 0, -125] DstBlock "Bus\nCreator" DstPort 14 } Line { SrcBlock "Extract Bits13" SrcPort 1 Points [25, 0; 0, -35; 215, 0; 0, -125] DstBlock "Bus\nCreator" DstPort 15 } Line { SrcBlock "Data Type Conversion10" SrcPort 1 Points [40, 0; 0, 45; 205, 0] Branch { Points [0, -55] DstBlock "Extract Bits14" DstPort 1 } Branch { DstBlock "Extract Bits15" DstPort 1 } } Line { SrcBlock "Extract Bits14" SrcPort 1 Points [110, 0; 0, -140] DstBlock "Bus\nCreator" DstPort 16 } Line { SrcBlock "Extract Bits15" SrcPort 1 Points [125, 0; 0, -185] DstBlock "Bus\nCreator" DstPort 17 } Line { SrcBlock "Signal1" SrcPort 1 DstBlock "Data Type Conversion1" DstPort 1 } Line { SrcBlock "Signal2" SrcPort 1 DstBlock "Data Type Conversion2" DstPort 1 } Line { SrcBlock "Signal3" SrcPort 1 DstBlock "Data Type Conversion4" DstPort 1 } Line { SrcBlock "Signal4" SrcPort 1 DstBlock "Data Type Conversion6" DstPort 1 } Line { SrcBlock "Signal5" SrcPort 1 DstBlock "Data Type Conversion7" DstPort 1 } Line { SrcBlock "Signal6" SrcPort 1 DstBlock "Data Type Conversion8" DstPort 1 } Line { SrcBlock "Signal7" SrcPort 1 DstBlock "Data Type Conversion9" DstPort 1 } Line { SrcBlock "Signal8" SrcPort 1 DstBlock "Data Type Conversion10" DstPort 1 } } } Block { BlockType Sum Name "Sum" SID "841" Ports [2, 1] Position [665, 280, 685, 300] ShowName off IconShape "round" Inputs "|++" InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Sum1" SID "843" Ports [2, 1] Position [665, 230, 685, 250] ShowName off IconShape "round" Inputs "|++" InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Sum2" SID "858" Ports [2, 1] Position [665, 330, 685, 350] ShowName off IconShape "round" Inputs "|++" InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Sum3" SID "862" Ports [2, 1] Position [665, 380, 685, 400] ShowName off IconShape "round" Inputs "|++" InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Sum4" SID "851" Ports [2, 1] Position [665, 430, 685, 450] ShowName off IconShape "round" Inputs "|++" InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Sum5" SID "864" Ports [2, 1] Position [665, 480, 685, 500] ShowName off IconShape "round" Inputs "|++" InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Sum6" SID "867" Ports [2, 1] Position [665, 530, 685, 550] ShowName off IconShape "round" Inputs "|++" InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Sum Name "Sum7" SID "869" Ports [2, 1] Position [665, 590, 685, 610] ShowName off IconShape "round" Inputs "|++" InputSameDT off OutDataTypeStr "Inherit: Inherit via internal rule" SaturateOnIntegerOverflow off } Block { BlockType Reference Name "UART Configuration" SID "781" Tag "dsPIC_config_UART" Ports [] Position [265, 28, 365, 78] BackgroundColor "lightBlue" DropShadow on Priority "2" LibraryVersion "3.79" SourceBlock "dsPICdrivers/Serial PORT/UART Configuration" SourceType "Configure UART" UART "2" proposed_BAUD "Custom" BAUD "128000" ALT_TX_RX off InterruptTxWhen "When Transmit Buffer is empty" TXInterruptPri "1" TxBufferSize "1024" TXEN on InterruptRxWhen "When Receive Buffer is full (contain 4 characters)" RXInterruptPri "2" RxBufferSize "1024" DoNotImplementRxInterrupt off DoNotImplementTxInterrupt off UxBRG "19" Info "UxBRG = 19 || Real Baud : 125000 || % error : -2.3438 || max 12.5 Bytes / Step" RealBaud "0" ERROR "-2.3438" BYTES_STEP "12.5" } Block { BlockType SubSystem Name "eDum_Right" SID "634" Ports [2, 2] Position [710, 16, 880, 194] ZOrder -1 LibraryVersion "1.251" ErrorFcn "Stateflow.Translate.translate" PermitHierarchicalResolution "ExplicitOnly" TreatAsAtomicUnit on MinAlgLoopOccurrences off PropExecContextOutsideSubsystem off RTWSystemCode "Auto" FunctionWithSeparateData off Opaque off RequestExecContextInheritance off MaskHideContents off MaskType "Stateflow" MaskDescription "Stateflow diagram" MaskSelfModifiable on MaskDisplay "plot(sf('Private','sfblk','xIcon'),sf('Private','sfblk','yIcon'));text(0.5,0,sf('Private', 's" "fblk', 'tIcon'),'HorizontalAl','Center','VerticalAl','Bottom');" MaskIconFrame off MaskIconOpaque off MaskIconRotate "none" MaskPortRotate "default" MaskIconUnits "autoscale" System { Name "eDum_Right" Location [257, 457, 812, 717] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "A4" PaperUnits "centimeters" TiledPaperMargins [1.270000, 1.270000, 1.270000, 1.270000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" SIDHighWatermark "55" Block { BlockType Inport Name "Switch" SID "634::48" Position [20, 101, 40, 119] IconDisplay "Port number" } Block { BlockType Inport Name "Current" SID "634::55" Position [20, 136, 40, 154] Port "2" IconDisplay "Port number" } Block { BlockType Demux Name " Demux " SID "634::44" Ports [1, 1] Position [270, 225, 320, 265] Outputs "1" } Block { BlockType S-Function Name " SFunction " SID "634::43" Tag "Stateflow S-Function uC_Stateflow_after 2" Ports [2, 3] Position [180, 105, 230, 225] FunctionName "sf_sfun" PortCounts "[2 3]" EnableBusSupport on Port { PortNumber 2 Name "TTL_R1" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } Port { PortNumber 3 Name "TTL_R2" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Terminator Name " Terminator " SID "634::46" Position [460, 236, 480, 254] } Block { BlockType Outport Name "TTL_R1" SID "634::53" Position [460, 101, 480, 119] IconDisplay "Port number" } Block { BlockType Outport Name "TTL_R2" SID "634::54" Position [460, 136, 480, 154] Port "2" IconDisplay "Port number" } Line { SrcBlock "Switch" SrcPort 1 DstBlock " SFunction " DstPort 1 } Line { SrcBlock "Current" SrcPort 1 DstBlock " SFunction " DstPort 2 } Line { Name "TTL_R1" Labels [0, 0; 0, 0] SrcBlock " SFunction " SrcPort 2 DstBlock "TTL_R1" DstPort 1 } Line { Name "TTL_R2" Labels [0, 0; 0, 0] SrcBlock " SFunction " SrcPort 3 DstBlock "TTL_R2" DstPort 1 } Line { SrcBlock " Demux " SrcPort 1 DstBlock " Terminator " DstPort 1 } Line { SrcBlock " SFunction " SrcPort 1 DstBlock " Demux " DstPort 1 } } } Line { SrcBlock "Digital Input1" SrcPort 1 DstBlock "Data Type Conversion4" DstPort 1 } Line { SrcBlock "Data Type Conversion4" SrcPort 1 DstBlock "Rate Transition1" DstPort 1 } Line { SrcBlock "Data Type Conversion1" SrcPort 1 Points [15, 0] DstBlock "Digital Output Write2" DstPort 1 } Line { SrcBlock "Data Type Conversion2" SrcPort 1 Points [15, 0] DstBlock "Digital Output Write2" DstPort 2 } Line { SrcBlock "eDum_Right" SrcPort 1 DstBlock "Rate Transition2" DstPort 1 } Line { SrcBlock "ADC Input" SrcPort 1 DstBlock "Data Type Conversion7" DstPort 1 } Line { SrcBlock "Data Type Conversion7" SrcPort 1 DstBlock "Filtrage de Kalman2" DstPort 1 } Line { SrcBlock "ADC Input" SrcPort 2 DstBlock "Data Type Conversion5" DstPort 1 } Line { SrcBlock "ADC Input" SrcPort 3 DstBlock "Data Type Conversion6" DstPort 1 } Line { SrcBlock "Data Type Conversion5" SrcPort 1 Points [15, 0] DstBlock "Add" DstPort 1 } Line { SrcBlock "Data Type Conversion6" SrcPort 1 Points [15, 0] DstBlock "Add" DstPort 2 } Line { SrcBlock "Add" SrcPort 1 DstBlock "Filtrage de Kalman2" DstPort 2 } Line { SrcBlock "Gain1" SrcPort 1 DstBlock "Sum" DstPort 1 } Line { SrcBlock "Sum" SrcPort 1 DstBlock "Serial Communication\nUART" DstPort 2 } Line { SrcBlock "Sum1" SrcPort 1 DstBlock "Serial Communication\nUART" DstPort 1 } Line { SrcBlock "Sum4" SrcPort 1 DstBlock "Serial Communication\nUART" DstPort 5 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Sum1" DstPort 2 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "Sum" DstPort 2 } Line { SrcBlock "Constant" SrcPort 1 DstBlock "Sum4" DstPort 2 } Line { SrcBlock "Filtrage de Kalman2" SrcPort 1 Points [0, -35] DstBlock "Gain2" DstPort 1 } Line { SrcBlock "Gain2" SrcPort 1 DstBlock "Rate Transition4" DstPort 1 } Line { SrcBlock "Gain3" SrcPort 1 DstBlock "Sum2" DstPort 1 } Line { SrcBlock "Constant3" SrcPort 1 DstBlock "Sum2" DstPort 2 } Line { SrcBlock "Sum2" SrcPort 1 DstBlock "Serial Communication\nUART" DstPort 3 } Line { SrcBlock "Gain5" SrcPort 1 DstBlock "Sum3" DstPort 1 } Line { SrcBlock "Constant4" SrcPort 1 DstBlock "Sum3" DstPort 2 } Line { SrcBlock "Sum3" SrcPort 1 DstBlock "Serial Communication\nUART" DstPort 4 } Line { SrcBlock "Constant5" SrcPort 1 DstBlock "Sum5" DstPort 2 } Line { SrcBlock "Sum5" SrcPort 1 DstBlock "Serial Communication\nUART" DstPort 6 } Line { SrcBlock "Constant6" SrcPort 1 DstBlock "Sum6" DstPort 2 } Line { SrcBlock "Sum6" SrcPort 1 DstBlock "Serial Communication\nUART" DstPort 7 } Line { SrcBlock "Constant7" SrcPort 1 DstBlock "Sum7" DstPort 2 } Line { SrcBlock "Sum7" SrcPort 1 Points [25, 0] DstBlock "Serial Communication\nUART" DstPort 8 } Line { SrcBlock "eDum_Right" SrcPort 2 DstBlock "Rate Transition3" DstPort 1 } Line { SrcBlock "Gain9" SrcPort 1 DstBlock "Sum4" DstPort 1 } Line { SrcBlock "Gain8" SrcPort 1 DstBlock "Sum6" DstPort 1 } Line { SrcBlock "Gain4" SrcPort 1 DstBlock "Sum5" DstPort 1 } Line { SrcBlock "Gain6" SrcPort 1 DstBlock "Sum7" DstPort 1 } Line { SrcBlock "Gain14" SrcPort 1 DstBlock "Sum1" DstPort 1 } Line { SrcBlock "Rate Transition1" SrcPort 1 DstBlock "eDum_Right" DstPort 1 } Line { SrcBlock "Rate Transition4" SrcPort 1 DstBlock "eDum_Right" DstPort 2 } Line { SrcBlock "Rate Transition2" SrcPort 1 DstBlock "Data Type Conversion1" DstPort 1 } Line { SrcBlock "Rate Transition3" SrcPort 1 DstBlock "Data Type Conversion2" DstPort 1 } Line { SrcBlock "Filtrage de Kalman2" SrcPort 2 DstBlock "Gain14" DstPort 1 } Line { SrcBlock "Filtrage de Kalman2" SrcPort 3 Points [0, -5] DstBlock "Gain1" DstPort 1 } } } # Finite State Machines # # Stateflow Version 7.5 (R2010a) dated Mar 5 2011, 00:01:50 # # Stateflow { machine { id 1 name "uC_Stateflow_after" created "31-Jan-2013 09:53:58" isLibrary 0 firstTarget 27 sfVersion 75014001 } chart { id 2 name "Filtrage de Kalman2" windowPosition [461.931 122.698 200.25 189.75] viewLimits [0 156.75 0 153.75] screen [1 1 1280 800 1.333333333333333] treeNode [0 3 0 0] firstTransition 5 firstJunction 4 viewObj 2 machine 1 ssIdHighWaterMark 93 decomposition CLUSTER_CHART type EML_CHART firstData 6 chartFileNumber 1 disableImplicitCasting 1 eml { name "fcn" } } state { id 3 labelString "eML_blk_kernel()" position [18 64.5 118 66] fontSize 12 chart 2 treeNode [2 0 0 0] superState SUBCHART subviewer 2 ssIdNumber 1 type FUNC_STATE decomposition CLUSTER_STATE eml { isEML 1 script "function [Z1,Voltage1,Z2] = fcn(Z,Voltage)\n\n\nVoltage=(Voltage*0.004);\nVoltage1=Voltage;\nZ=(5" "0/12412)*Z;\nif Voltage<=-0.3\n Z=-Z;\nelse\nend\nZ1=Z;\nZ2=Z;\n\n\n\n\n\n\n \n" editorLayout "100 M4x1[545 164 720 481]" } } junction { id 4 position [23.5747 49.5747 7] chart 2 linkNode [2 0 0] subviewer 2 ssIdNumber 3 type CONNECTIVE_JUNCTION } transition { id 5 labelString "{eML_blk_kernel();}" labelPosition [32.125 19.875 102.544 14.964] fontSize 12 src { intersection [0 0 1 0 23.5747 14.625 0 0] } dst { id 4 intersection [7 0 -1 -1 23.5747 42.5747 0 0] } midPoint [23.5747 24.9468] chart 2 linkNode [2 0 0] dataLimits [23.575 23.575 14.625 34.575] subviewer 2 drawStyle SMART executionOrder 1 ssIdNumber 2 } data { id 6 ssIdNumber 46 name "Z1" linkNode [2 0 7] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 7 ssIdNumber 65 name "Voltage1" linkNode [2 6 8] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 8 ssIdNumber 85 name "Z2" linkNode [2 7 9] scope OUTPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 9 ssIdNumber 37 name "Z" linkNode [2 8 10] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } data { id 10 ssIdNumber 36 name "Voltage" linkNode [2 9 0] scope INPUT_DATA machine 1 props { array { size "-1" } type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } complexity SF_COMPLEX_INHERITED frame SF_FRAME_INHERITED } dataType "Inherit: Same as Simulink" } instance { id 11 name "Filtrage de Kalman2" machine 1 chart 2 } chart { id 12 name "eDum_Right" windowPosition [18.75 24.75 960 519] viewLimits [303.15 1219.65 256.285 739.285] screen [1 1 1280 800 1.333333333333333] treeNode [0 13 0 0] firstTransition 18 viewObj 12 visible 1 machine 1 subviewS { x1 303.15 y1 256.285 } ssIdHighWaterMark 93 decomposition CLUSTER_CHART firstData 22 updateMethod DISCRETE sampleTime "0.01" chartFileNumber 2 userSpecifiedStateTransitionExecutionOrder 1 disableImplicitCasting 1 actionLanguage 1 } state { id 13 labelString "Clockwise1\nentry: TTL_R1=1;\nTTL_R2=1;" position [866.4976 313.8769 144.125 67.125] fontSize 12 chart 12 treeNode [12 0 0 16] subviewer 12 ssIdNumber 79 type OR_STATE decomposition CLUSTER_STATE } state { id 14 labelString "Counterclockwise1\nentry: TTL_R1=1;\nTTL_R2=0;" position [439.5409 438.7974 144.125 67.125] fontSize 12 chart 12 treeNode [12 0 16 15] superState GROUPED subviewer 12 ssIdNumber 78 type OR_STATE decomposition CLUSTER_STATE } state { id 15 labelString "Break3\nentry: TTL_R1=0;\nTTL_R2=0;" position [868.2278 438.8769 144.125 67.125] fontSize 12 chart 12 treeNode [12 0 14 0] subviewer 12 ssIdNumber 77 type OR_STATE decomposition CLUSTER_STATE } state { id 16 labelString "Break1\nentry: TTL_R1=0;\nTTL_R2=0;" position [440.002 317.1138 144.125 67.125] fontSize 12 chart 12 treeNode [12 0 13 14] subviewer 12 ssIdNumber 76 type OR_STATE decomposition CLUSTER_STATE } transition { id 17 labelString "[after(10,tick) && Switch==1]" labelPosition [354.348 409.145 149.927 14.971] fontSize 12 src { id 16 intersection [3 0 1 0.5098 510.6501 384.2388 0 1.4144] } dst { id 14 intersection [1 0 -1 0.4934 510.6501 438.7974 0 -1.4144] } midPoint [510.6501 408.4435] chart 12 linkNode [12 21 20] dataLimits [508.25 513.05 384.239 438.797] stampAngle NaN subviewer 12 drawStyle SMART slide { } executionOrder 1 ssIdNumber 85 } transition { id 18 labelPosition [385.053 343.264 8.246 14.971] fontSize 12 src { intersection [0 1 0 0.5298 362.8846 342.8789 0 -55.5] } dst { id 16 intersection [4 -1 0 0.6162 440.002 342.8789 0 72.75] } midPoint [398.8591 342.8789] chart 12 linkNode [12 0 21] dataLimits [362.885 440.002 340.479 345.279] stampAngle NaN subviewer 12 drawStyle SMART executionOrder 1 ssIdNumber 81 } transition { id 19 labelString "[after(300,tick) || (Current>=100 && after(20,tick))]" labelPosition [596.073 472.468 257.126 14.971] fontSize 12 src { id 14 intersection [2 1 0 0.443 583.6659 468.5354 0 -3.8245] } dst { id 15 intersection [4 -1 0 0.5582 868.2278 468.5354 0 3.8245] } midPoint [727.8723 468.5354] chart 12 linkNode [12 20 0] dataLimits [583.666 868.228 466.135 470.935] stampAngle NaN subviewer 12 drawStyle SMART slide { } executionOrder 1 ssIdNumber 86 } transition { id 20 labelString "[after(10,tick) && Switch==1]" labelPosition [933.94 409.854 149.927 14.971] fontSize 12 src { id 15 intersection [1 0 -1 0.4435 932.1501 438.8769 0 4.8598] } dst { intersection [0 0 1 0.0787 932.1501 387.5354 0 -4.8598] } midPoint [932.1501 416.3507] chart 12 linkNode [12 17 19] dataLimits [929.75 934.55 387.535 438.877] stampAngle NaN subviewer 12 drawStyle SMART slide { } executionOrder 1 ssIdNumber 88 } transition { id 21 labelString "[after(200,tick)]" labelPosition [694.262 334.086 79.462 14.971] fontSize 12 src { id 13 intersection [4 -1 0 0.4055 866.4976 353.7854 0 -6.346] } dst { id 16 intersection [2 1 0 0.5463 584.127 353.7854 0 6.346] } midPoint [723.4345 353.7854] chart 12 linkNode [12 18 17] dataLimits [584.127 866.498 351.385 356.185] stampAngle NaN subviewer 12 drawStyle SMART slide { } executionOrder 1 ssIdNumber 87 } data { id 22 ssIdNumber 42 name "Switch" linkNode [12 0 23] scope INPUT_DATA machine 1 props { type { method SF_INHERITED_TYPE primitive SF_UINT8_TYPE isSigned 1 wordLength "16" } frame SF_FRAME_NO } dataType "Inherit: Same as Simulink" } data { id 23 ssIdNumber 71 name "TTL_R1" linkNode [12 22 24] scope OUTPUT_DATA machine 1 props { type { primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } frame SF_FRAME_NO } dataType "double" } data { id 24 ssIdNumber 72 name "TTL_R2" linkNode [12 23 25] scope OUTPUT_DATA machine 1 props { type { primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } frame SF_FRAME_NO } dataType "double" } data { id 25 ssIdNumber 90 name "Current" linkNode [12 24 0] scope INPUT_DATA machine 1 props { type { method SF_INHERITED_TYPE primitive SF_DOUBLE_TYPE isSigned 1 wordLength "16" } } dataType "Inherit: Same as Simulink" } instance { id 26 name "eDum_Right" machine 1 chart 12 } target { id 27 name "sfun" description "Default Simulink S-Function Target." machine 1 linkNode [1 0 28] } target { id 28 name "rtw" machine 1 linkNode [1 27 0] } }